期刊名称：International Journal of Electronics Communication and Computer Technology
印刷版ISSN：2249-7838
出版年度：2013
卷号：3
期号：5
页码：485-488
出版社：International Journal of Electronics Communication and Computer Technology
摘要：Purpose: CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare the two technologies [1]. Low pow er static-random access memories (SRAM) have become a critical co mponent in modern VLSI systems. They occupy a large portion of area and accounts for a major component of power consumption in today's VLSI circuits. In this paper we intend to analyse the performance of a traditional 6T SRAM cell of 16nm Complementary Metal Oxide Semiconductor (CMOS) technology with change in Operating Voltage and Temperature. Aim: The aim of the paper is to study the effect of the SNM dependencies on the operating voltage and temperature Approach: Conventional 6T SRAM are designed using predictive technology model developed by Arizona State University [2] of 16nm planar Low Power CMOS and variation of SNM with operating voltage and temperature are simulated and studied using hspice. Findings: Variations in the operating voltages and temperature strongly impact the stability of an SRAM cell at 16nm. Comparative study is done for predictive 16nm based conventional 6T SRAM cell by varying operating voltage and temperature. A methodology to select operating voltage is suggested which can be used in an early stage of a design cycle to optimise stability margins in nanometer regime
关键词：SRAM; Static Noise Margin; operating ;voltage; temperature
