期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2014
卷号：3
期号：1
页码：76-85
出版社：Buldanshahr : IJECSE
摘要：We present in this paper a new model of a low pass filter (LPF) for a Phase-Locked Loop (PLL) systems. The main characteristic of this CMOS LPF structure is its dynamic band-width (about 12.66kHz when the PLL is locked and 211. 30kHz during the tracking). It ensures a fast response time, a suppression of the jitters and a better noise level at the output. This LPF polarization is ensured by the current from the PFC-IC (Phase-Frequency Comparator with Charge Impulse) and the VCO control voltage. The simulation in a PLL system gives us a response time of 35.4 μs and a phase noise level of -121.37dBc. Significant improvements could be expected with a dedicated CMOS process and design
