摘要：This paper describes the hardware
implementation of the RANdom Sample Consensus (RANSAC) algorithm for featured-based
image registration applications. The Multiple-Input Signature Register (MISR)
and the index register are used to achieve the random sampling effect. The
systolic array architecture is adopted to implement the forward elimination
step in the Gaussian elimination. The computational complexity in the forward
elimination is reduced by sharing the coefficient matrix. As a result, the area
of the hardware cost is reduced by more than 50%. The proposed architecture is realized
using Verilog and achieves real-time calculation on 30 fps 1024 * 1024 video stream on 100
MHz clock.
