摘要：In general, a large number of different Intellectual Property (IP) cores can be implemented on a System-On-Chip (SOC) in parallel. However, this was not resource efficient, as depending on the application, only a subset of those cores would active at the same time. This study focused on the design method of the Dynamic Partial Reconfigurable (DPR) system that design and implements a DPR system to address the problems. The result of experiment shows that DPR can greatly improve FPGA’s resource utilization and save reconfigurable time.
