摘要：This article described a complete design of parallel interface based on ARM & FPGA, using the on-chip DPRAM in FPGA to improve the metastability problem which was generated during data transmission between the asynchronous clock-domains; And it achieved the design of ARM & FPGA hardware interface module , data-sending module , data-receiving module and FPGA driver module , also gave the feasible method that using a flag to solve the dislocation of data-reading; Test results indicate that the system works steadily.
关键词：ARM; FPGA; Parallel Data Interface; metastability
