1.Improvement of Voltage Profile through the Optimal Placement of FACTS Using L-Index Method

作　　者：K. Venkata Ramana Reddy ;M. Padma Lalitha ;PB Chennaiah

出　　处：International Journal of Electrical and Computer Engineering. 2014 ;4(2):207-211.doi:10.11591/ijece.v4i2.5136

出版社：Institute of Advanced Engineering and Science (IAES)

文章 ID：100030082

文章详细全文下载
2.Siting and Sizing of DG for Loss Reduction and Voltage Sag Mitigation in RDS Using ABC Algorithm

作　　者：Kuruva Siva Ramudu ;M. Padma Lalitha ;P. Suresh Babu

出　　处：International Journal of Electrical and Computer Engineering. 2013 ;3(6):814-822.doi:10.11591/ijece.v3i6.4399

出版社：Institute of Advanced Engineering and Science (IAES)

文章 ID：100030193

文章详细全文下载
3.Improvement of Voltage Profile through the Optimal Placement of FACTS Using L-Index Method

作　　者：K. Venkata Ramana Reddy ;M. Padma Lalitha ;PB Chennaiah

出　　处：International Journal of Electrical and Computer Engineering. 2014 ;4(2):207-211.

出版社：Institute of Advanced Engineering and Science (IAES)

文章 ID：218175208

文章详细
4.Siting and Sizing of DG for Loss Reduction and Voltage Sag Mitigation in RDS Using ABC Algorithm

作　　者：Kuruva Siva Ramudu ;M. Padma Lalitha ;P. Suresh Babu

出　　处：International Journal of Electrical and Computer Engineering. 2013 ;3(6):814-822.

出版社：Institute of Advanced Engineering and Science (IAES)

文章 ID：218175250

文章详细

	有全文链接	2篇
	有本地全文	2篇

全文

出版年度

作者

来源期刊

学科主题

语种

国别/地区

检索条件:"( ( 高级检索(( ((AU:(("M. Padma Lalitha")))) )) ) )"

	M. Padma Lalitha	4篇
	K. Venkata Ramana Reddy	2篇
	Kuruva Siva Ramudu	2篇
	P. Suresh Babu	2篇
	PB Chennaiah	2篇

	2014	2篇
	2013	2篇