1.Design and Functional Verification of A SPI Master Slave Core Using System Verilog

作　　者：K.Aditya ;M.Sivakumar ;Fazal Noorbasha 等

出　　处：International Journal of Soft Computing & Engineering. 2012 ;2(2):558-563.

出版社：International Journal of Soft Computing & Engineering

文章 ID：86825509

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2.Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

作　　者：Abdul Kareem PARCHUR ;Kuppangari Krishna RAO ;Fazal NOORBASHA 等

出　　处：Leonardo Electronic Journal of Practices and Technologies. 2010 ;9(17):109-116.

出版社：Academic Direct Publishing House

文章 ID：47792746

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3.COMPARATIVE ANALYSIS OF CORDIC ALGORITHM AND TAYLOR SERIES EXPANSION

作　　者：M. MANASA ;FAZAL NOORBASHA ;CH.L.SUDHESHNA 等

出　　处：Journal of Theoretical and Applied Information Technology. 2017 ;95(9).

出版社：Journal of Theoretical and Applied

文章 ID：200781982

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4.FPGA IMPLEMENTATION OF CRYPTOGRAPHIC SYSTEMS FOR SYMMETRIC ENCRYPTION

作　　者：FAZAL NOORBASHA ;M. MANASA ;R. TULASI GOUTHAMI 等

出　　处：Journal of Theoretical and Applied Information Technology. 2017 ;95(9).

出版社：Journal of Theoretical and Applied

文章 ID：200781985

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5.Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA

作　　者：Narendra Babu T ;Fazal Noorbasha ;Leenendra Chowdary Gunnam

出　　处：International Journal of Electrical and Computer Engineering. 2016 ;6(2):602-610.doi:10.11591/ijece.v6i2.pp602-610

出版社：Institute of Advanced Engineering and Science (IAES)

文章 ID：186756799

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6.VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

作　　者：Fazal NOORBASHA

出　　处：Leonardo Electronic Journal of Practices and Technologies. 2011 ;10(19):133-143.

出版社：Academic Direct Publishing House

文章 ID：190831745

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7.VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

作　　者：Fazal NOORBASHA

出　　处：Leonardo Electronic Journal of Practices and Technologies. 2011 ;10(19):133-143.

出版社：Academic Direct Publishing House

文章 ID：190837518

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8.Architecture Approach for Scalable Encryption Algorithm and Implementation in FPGA

作　　者：K.Rajasekhar ;S.Adilakshmi ;Dr. Fazal Noorbasha 等

出　　处：International Journal of Computer Science & Technology. 2012 ;3(2):434-438.

出版社：Ayushmaan Technologies

文章 ID：1025574054

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	M. MANASA	2篇
	MD. ZIA UR RAHMAN	2篇

	Abdul Kareem PARCHUR	1篇
	CH.L.SUDHESHNA	1篇
	D. HARI PRIYA	1篇
	Dr. Fazal Noorbasha	1篇
	K.Aditya	1篇
	K.Rajasekhar	1篇
	Kuppangari Krishna RAO	1篇
	Leenendra Chowdary Gunnam	1篇
	M.SANTHOSH	1篇
	M.Sivakumar	1篇
	N. PRASHANTH	1篇
	Narendra Babu T	1篇
	R. TULASI GOUTHAMI	1篇
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	S. SRUTHI	1篇
	S.Adilakshmi	1篇
	T.B.K Manoj Kumar	1篇
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	Leonardo Electronic Journal of Practices and Technologies	3篇
	Journal of Theoretical and Applied Information Technology	2篇
	International Journal of Computer Science & Technology	1篇
	International Journal of Electrical and Computer Engineering	1篇
	International Journal of Soft Computing & Engineering	1篇

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