1.Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

作　　者：Zhao Lei ;Daisuke Ikebuchi ;Kimiyoshi Usami 等

出　　处：Information and Media Technologies. 2011 ;6(4):1092-1102.doi:10.11185/imt.6.1092

出版社：Information and Media Technologies Editorial Board

文章 ID：103885927

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2.A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

作　　者：Mai Izawa ;Nobuaki Ozaki ;Yusuke Koizumi 等

出　　处：International Journal of Networking and Computing. 2015 ;5(1):239-251.

出版社：International Journal of Networking and Computing

文章 ID：100361828

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3.Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

作　　者：Mohamad Sofian Abu Talip ;Takayuki Akamine ;Mao Hatto 等

出　　处：International Journal of Networking and Computing. 2013 ;3(2):289-306.

出版社：International Journal of Networking and Computing

文章 ID：100361832

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4.Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

作　　者：Akio Nomura ;Yusuke Matsushita ;Junichiro Kadomoto 等

出　　处：International Journal of Networking and Computing. 2018 ;8(1):124-139.

出版社：International Journal of Networking and Computing

文章 ID：208617134

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5.An implementation methodology for Neural Network on a Low-end FPGA Board

作　　者：Kaijie Wei ;Koki Honda ;Hideharu Amano

出　　处：International Journal of Networking and Computing. 2021 ;11(2):172-197.

出版社：International Journal of Networking and Computing

文章 ID：1037085620

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