1.ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT

作　　者：P.Nirmalkumar ;J.Raja Paul Perinbam, S.Ravi ;B.Rajan

出　　处：International Journal of Computer Science and Network Security. 2006 ;6(9A):216-222.

出版社：International Journal of Computer Science and Network Security

文章 ID：46398749

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2.Coarse Grained Reconfigurable Architectures for Motion Estimation in H.264/avc

作　　者：D.rukmani Devi ;P.rangarajan ;J.raja Paul Perinbam

出　　处：Journal of Theoretical and Applied Information Technology. 2010 ;15(02).

出版社：Journal of Theoretical and Applied

文章 ID：47603342

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3.A DOUBLE GUARD HILL CIPHER SUITABLE FOR WIRELESS SENSOR NETWORKS

作　　者：C.BENNILA THANGAMMAL ;P.RANGARAJAN ;J.RAJA PAUL PERINBAM

出　　处：Journal of Theoretical and Applied Information Technology. 2013 ;57(1).

出版社：Journal of Theoretical and Applied

文章 ID：187139182

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4.A New Reconfigurable Hardware Architecture for Cryptography Applications using AES by different Substitution box (S-Box) and Random Round Selection

作　　者：G.Venkatesan ;J.Raja Paul Perinbam

出　　处：International Journal of Computer Science and Network Security. 2011 ;11(12):112-116.

出版社：International Journal of Computer Science and Network Security

文章 ID：186858910

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	B.Rajan	1篇
	C.BENNILA THANGAMMAL	1篇
	D.rukmani Devi	1篇
	G.Venkatesan	1篇
	J.RAJA PAUL PERINBAM	1篇

	J.Raja Paul Perinbam	1篇
	J.Raja Paul Perinbam, S.Ravi	1篇
	J.raja Paul Perinbam	1篇
	P.Nirmalkumar	1篇
	P.RANGARAJAN	1篇
	P.rangarajan	1篇

	International Journal of Computer Science and Network Security	2篇
	Journal of Theoretical and Applied Information Technology	2篇

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