1.Two-level AND-XOR Network Synthesis with Area-Power Trade-off

作　　者：Sambhu Nath Pradhan ;Santanu Chattopadhyay

出　　处：International Journal of Computer Science and Network Security. 2008 ;8(9):365-374.

出版社：International Journal of Computer Science and Network Security

文章 ID：46920173

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2.System-on-Chip Test-time and Scan-power Minimization Integrating Core and Interconnect Testing

作　　者：Gautam Das ;Santanu Chattopadhyay ;Haripada Bhaumik

出　　处：International Journal of Computer Science and Network Security. 2009 ;9(3):201-209.

出版社：International Journal of Computer Science and Network Security

文章 ID：46960586

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3.Two-level AND-XOR Network Synthesis with Area-Power Trade-off

作　　者：Sambhu Nath Pradhan ;Santanu Chattopadhyay

出　　处：International Journal of Computer Science and Network Security. 2008 ;8(9):365-374.

出版社：International Journal of Computer Science and Network Security

文章 ID：186860992

文章详细
4.System-on-Chip Test-time and Scan-power Minimization Integrating Core and Interconnect Testing

作　　者：Gautam Das ;Santanu Chattopadhyay ;Haripada Bhaumik

出　　处：International Journal of Computer Science and Network Security. 2009 ;9(3):201-209.

出版社：International Journal of Computer Science and Network Security

文章 ID：186861203

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检索条件:"( ( 高级检索(( ((AU:(("Santanu Chattopadhyay")))) )) ) )"

	Santanu Chattopadhyay	4篇
	Gautam Das	2篇
	Haripada Bhaumik	2篇
	Sambhu Nath Pradhan	2篇

	2009	2篇
	2008	2篇