1.Row-Based Dual <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-4.62607pt;width:33.950001px;" id="M1" height="20.262501" version="1.1" viewBox="0 0 33.950001 20.262501" width="33.950001"> <g transform="matrix(.022,-0,0,-.022,.062,14.638)"><path id="x1D449" d="M730 650l-8 -28q-52 -4 -72 -18t-64 -77q-79 -113 -321 -539h-33l-119 541q-13 59 -29.5 73t-66.5 20l7 28h245l-8 -28l-28 -5q-33 -6 -40.5 -15.5t-0.5 -38.5l102 -450h2q191 320 246 430q21 42 15.5 56t-43.5 19l-31 4l7 28h240z"></path></g> <g transform="matrix(.016,-0,0,-.016,16.7,20.012)"><path id="x64" d="M517 51v-25q-101 -18 -155 -38v65l-61 -36q-50 -29 -78 -29q-68 0 -126.5 58t-58.5 155q0 103 77 175.5t180 72.5q36 0 67 -12v143q0 48 -11.5 58.5t-65.5 14.5v25q79 9 156 34v-597q0 -38 7.5 -48t36.5 -13zM362 85v275q-35 51 -103 51q-20 0 -40.5 -8.5t-42 -28
t-35 -57.5t-13.5 -89q0 -83 42 -130t96 -47q51 0 96 34z"></path></g><g transform="matrix(.016,-0,0,-.016,24.985,20.012)"><use xlink:href="#x64"></use></g> </svg> Assignment, for a Level Converter Free CSA Design and Its Near-Threshold Operation

作　　者：Dipankar Saha ;Aanan Chatterjee ;Sayan Chatterjee 等

出　　处：Advances in Electrical Engineering. 2014 ;2014.doi:10.1155/2014/814975

出版社：Hindawi Publishing Corporation

文章 ID：91459719

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2.Study and Analysis of Full Adder in Different Sub-Micron Technologies with an Area Efficient Layout of 4-Bit Ripple Carry Adder

作　　者：Sayan Chatterjee

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2015 ;3(6).doi:10.15680/ijircce.2015.0306005

出版社：S&S Publications

文章 ID：153305128

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3.The Low Cost Analogue Projector

作　　者：Sayan Chatterjee

出　　处：International Journal of Advances in Engineering and Management. 2021 ;3(8):1882-1884.doi:10.35629/5252-030817041710

出版社：IJAEM JOURNAL

文章 ID：1037737712

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