1.Line Topology Estimation of Indoor power Lines Using Multipoint Single Ended Loop Testing

作　　者：S. Ravishankar ;M. Bharathi

出　　处：International Journal of Future Generation Communication and Networking. 2012 ;5(3).

出版社：SERSC

文章 ID：87771857

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2.Design of Ladner-Fischer and Beaumont-Smith Adders Using Degenerate Pass Transistor Logic

作　　者：Adilakshmi Siliveru ;M. Bharathi

出　　处：International Journal of Soft Computing & Engineering. 2013 ;3(1):177-181.

出版社：International Journal of Soft Computing & Engineering

文章 ID：86825897

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3.A HIGH SPEED AND EFFICIENT DESIGN FOR BINARY NUMBER SQUARING USING DWANDWA YOGA

作　　者：B. Dilli kumar ;M. Bharathi

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2012 ;1(4):476-479.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：181212243

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4.LOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC

作　　者：B. Dilli kumar ;K. Charan kumar ;M. Bharathi

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2012 ;1(5):291-296.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：181212335

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5.Design of Energy Efficient Charge Recovery Digital Circuits Using Adiabatic Logic Techniques

作　　者：B. Dilli Kumar ;M. Bharathi

出　　处：International Journal of Computer Science & Technology. 2013 ;4(1):203-210.

出版社：Ayushmaan Technologies

文章 ID：1025546280

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	M. Bharathi	5篇
	B. Dilli kumar	2篇
	Adilakshmi Siliveru	1篇
	B. Dilli Kumar	1篇
	K. Charan kumar	1篇

	International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)	2篇
	International Journal of Computer Science & Technology	1篇
	International Journal of Future Generation Communication and Networking	1篇
	International Journal of Soft Computing & Engineering	1篇

	2013	2篇
	2012	3篇