1.Low Power-Area GDI & PTL Techniques Based Full Adder Designs

作　　者：Karthik Reddy.G ;Kavita Khare

出　　处：Computer Science & Information Technology. 2013 ;3(4):249-257.doi:10.5121/csit.2013.3426

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：88520534

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2.Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

作　　者：Arun Kumar Sunaniya ;Kavita Khare

出　　处：International Journal of VLSI Design & Communication Systems. 2013 ;4(3).

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：86826268

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3.Smart Multicrossbar Router Design in NOC

作　　者：Bhavana Prakash Shrivastava ;Kavita Khare

出　　处：International Journal of VLSI Design & Communication Systems. 2013 ;4(2).

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：86826277

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4.A Novel Power Reduction Technique for Dual-Threshold Domino Logic in Sub-65nm Technology

作　　者：Tarun Kr. Gupta ;Kavita Khare

出　　处：International Journal of VLSI Design & Communication Systems. 2013 ;4(1).

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：86826282

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5.Design and FPGA Implementation of DDR3 SDRAM Controller for High Performance

作　　者：Shabana Aqueel ;Kavita Khare

出　　处：International Journal of Computer Science & Information Technology (IJCSIT). 2011 ;3(4).

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：101193614

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6.Design of Improved Routers for Network on Chip

作　　者：Bhavana P.Shrivastava ;Kavita Khare

出　　处：International Journal of Computer Trends and Technology. 2013 ;4(9-1).

出版社：Seventh Sense Research Group

文章 ID：113424775

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7.Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

作　　者：Supriya Aggarwal ;Kavita Khare

出　　处：International Journal of Reconfigurable Computing. 2012 ;2012.doi:10.1155/2012/185784

出版社：Hindawi Publishing Corporation

文章 ID：79869447

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8.Efficient Absolute Difference Circuit for SAD Computation On FPGA

作　　者：Jaya Koshta ;Kavita Khare ;M.K Gupta

出　　处：International Journal of VLSI Design & Communication Systems. 2019 ;10(2):1-12.doi:10.5121/vlsic.2019.10201

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：243735915

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9.Efficient Absolute Difference Circuit for SAD Computation On FPGA

作　　者：Jaya Koshta ;Kavita Khare ;M.K Gupta

出　　处：International Journal of VLSI Design & Communication Systems. 2019 ;10(2):1-11.doi:10.5121/vlsic.2019.10201

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：243033409

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10.BackTrack Input Vector Algorithm for Leakage Reduction in CMOS VLSI Digital Circuit Design

作　　者：Uday Panwar ;Kavita Khare

出　　处：International Journal of VLSI Design & Communication Systems. 2014 ;5(2):1.doi:10.5121/vlsic.2014.5201

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：216765053

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	Kavita Khare	11篇
	Jaya Koshta	2篇
	M.K Gupta	2篇
	Ajay Kumar Dadoria	1篇
	Arun Kumar Sunaniya	1篇

	印度	10篇
	英国	1篇

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	Bhavana P.Shrivastava	1篇
	Bhavana Prakash Shrivastava	1篇
	Karthik Reddy.G	1篇
	Shabana Aqueel	1篇
	Supriya Aggarwal	1篇
	Tarun Kr. Gupta	1篇
	Uday Panwar	1篇

	International Journal of VLSI Design & Communication Systems	7篇
	Computer Science & Information Technology	1篇
	International Journal of Computer Science & Information Technology (IJCSIT)	1篇
	International Journal of Computer Trends and Technology	1篇
	International Journal of Reconfigurable Computing	1篇