1.VLSI Architecture for Reversible Multiplier-less Finite Impulse Response using Reversible Gate

作　　者：Yash Mishra ;Vaibhav Jindal

出　　处：International Journal of Innovative Research in Science, Engineering and Technology. 2018 ;7(6):6844-6850.doi:10.15680/IJIRSET.2018.0706073

出版社：S&S Publications

文章 ID：243724583

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2.VLSI Architecture for Complex Vedic Multiplier using Hybrid Square Kogge Stone Adder Technique

作　　者：Vivek Gupta ;Vaibhav Jindal

出　　处：International Journal of Innovative Research in Science, Engineering and Technology. 2018 ;7(6):7513-7520.doi:10.15680/IJIRSET.2018.0706125

出版社：S&S Publications

文章 ID：243724634

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3.Survey paper on FIR Filter using Programming Reversible Logic Gate

作　　者：Yash Mishra ;Prof. Vaibhav Jindal

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2018 ;6(6):6221-6226.doi:10.15680/IJIRCCE.2018.0606005

出版社：S&S Publications

文章 ID：243725140

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4.Review Paper on Hybrid Square Kogge Stone Adder and Vedic Multiplier Technique

作　　者：Vivek Gupta ;Prof. Vaibhav Jindal

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2018 ;6(6):6349-6355.doi:10.15680/IJIRCCE.2018.0606038

出版社：S&S Publications

文章 ID：243725174

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	社会学	2篇
	计算技术、计算机技术	2篇

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	Prof. Vaibhav Jindal	2篇
	Vaibhav Jindal	2篇
	Vivek Gupta	2篇
	Yash Mishra	2篇

	International Journal of Innovative Research in Computer and Communication Engineering	2篇
	International Journal of Innovative Research in Science, Engineering and Technology	2篇