1.Design and Implementation of Low Power Phase Lock Loop Using Sense Amplifier

作　　者：Anurag Bhatt ;Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2018 ;6(6):6239-6243.doi:10.15680/IJIRCCE.2018.0606008

出版社：S&S Publications

文章 ID：243725144

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2.Design a High Speed 16x16 CMOS Vedic Multiplier, For Different Configuration

作　　者：Praveen Kumar Sharma ;Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2018 ;6(6):6257-6262.doi:10.15680/IJIRCCE.2018.0606013

出版社：S&S Publications

文章 ID：243725149

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3.Low Power High Speed Body Bias Controlled Current Latch Sense Amplifier

作　　者：Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2018 ;6(10):8157-8164.doi:10.15680/IJIRCCE.2018. 0610034

出版社：S&S Publications

文章 ID：243725324

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4.Design and Implementation of Low Power FFT Processor for OFDM Wireless Communication

作　　者：Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2018 ;6(11):8617-8621.doi:10.15680/IJIRCCE.2018. 0611005

出版社：S&S Publications

文章 ID：243725339

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5.Design and Analysis of Novel Charge Pump Architecture for Phase Locked Loop

作　　者：Manoj Sharma ;Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2019 ;7(1):64-71.doi:10.15680/IJIRCCE.2019. 0701013

出版社：S&S Publications

文章 ID：243725427

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6.Low-Power and Area-Efficient Shift Register Using Pulsed Latches

作　　者：Jacob B Cacko ;Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2019 ;7(5):3155-3160.doi:10.15680/IJIRCCE.2019. 0705092

出版社：S&S Publications

文章 ID：243725671

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7.Low Power and High Performance Shift Registers Using Pulsed Latch Technique

作　　者：Jacob B Cacko ;Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2019 ;7(5):3161-3165.doi:10.15680/IJIRCCE.2019. 0705093

出版社：S&S Publications

文章 ID：243725672

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8.A Practical Framework for Energy-Efficient Node Activation in Heterogeneous LTE Networks

作　　者：Alok Kumar Bairwa ;Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2019 ;7(5):3191-3196.doi:10.15680/IJIRCCE.2019. 0705098

出版社：S&S Publications

文章 ID：243725678

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9.Analysis on Energy Efficient Traffic Load Balancing in Downlink LTE-Advanced Heterogeneous Network

作　　者：Alok Kumar Bairwa ;Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2019 ;7(5):3197-3202.doi:10.15680/IJIRCCE.2019. 0705099

出版社：S&S Publications

文章 ID：243725679

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10.Design and Analysis of Low Power Temperature Sensor using Static Latch D Flip-Flop

作　　者：Gangotri Pareek ;Gajendra Sujediya

出　　处：International Journal of Innovative Research in Computer and Communication Engineering. 2017 ;5(6):11473.doi:10.15680/IJIRCCE.2017.0506083

出版社：S&S Publications

文章 ID：215690564

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	Gajendra Sujediya	13篇
	Alok Kumar Bairwa	2篇
	Jacob B Cacko	2篇
	Pradeep Kumar Kumawat	2篇
	Praveen Kumar Sharma	2篇

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检索条件:"( ( 高级检索(( ((AU:(("Gajendra Sujediya")))) )) ) )"

	2019	5篇
	2018	4篇
	2017	4篇

	Anurag Bhatt	1篇
	Gangotri Pareek	1篇
	Manoj Sharma	1篇